1. Field of the Invention
The invention relates to a multi-phase clock generator. Particularly, the invention relates to a multi-phase clock generator inbuilt with two delay locked loops.
2. Description of Related Art
Generally, in an integrated circuit (IC), each clock period is equally divided into a plurality of phases, so that a digital circuit can select one of the phases to perform data sampling. In order to achieve the above function, the IC is generally configured with a multi-phase clock generator.
FIG. 1 is a block diagram of a conventional multi-phase clock generator. As shown in FIG. 1, the conventional multi-phase clock generator 100 generates an output clock signal clk12 with 256 phase selections according to a digital signal S1 with 8 bits. A delay locked loop 110 simultaneously generates 256 phase clock signals P0-P255 according to an input clock signal clk11. Moreover, a phase selector 120 selects and outputs one of the phase clock signals P0-P255 to serve as the output clock signal clk12 according to the digital signal S1. In other words, the multi-phase clock generator 100 is formed by the single delay locked loop 110 and the single phase selector 120. The delay locked loop 110 has to simultaneously generate 256 phase clock signals to make the multi-phase clock generator 100 achieve the 256 phase selections.
However, under the conventional structure, the delay locked loop 110 has to connect 256 delay devices in series for generating the 256 phase clock signals. Therefore, when a number of the divided phases is large, a layout area and power consumption of the conventional multi-phase clock generator 100 are relatively great and the maximum operating frequency of the whole circuit is even limited. Moreover, when the number of the divided phases is excessive, numbers of input buffers and multiplexers built in the phase selector 120 are also increased, which may further increase the layout area and the power consumption of the conventional multi-phase clock generator 100.